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One board in your PCB panel shows up with a giant X — and it's not a mistake.  It's the factory being honest: that board failed the electrical test (an open or short), so they marked it and kept the boards beside it.  What it means 👇 1️⃣ You don't pay for the X-out — extra panels fill your order 2️⃣ The SMT machine can't read a hand-drawn X 3️⃣ It needs a bad-mark or blocked fiducial to skip it 4️⃣ Accept X-outs and panels stay cheap 5️⃣ "Not allowed" rejects the whole panel — 5% to 50% more on HDI 6️⃣ At 2% defects, a 20-board panel has a 33% chance of an X — statistics, not a sloppy factory .#pcb #pcbdesign #pcbmanufacturing #hardwareengineering #electronicsengineering #pcbpanel #dfm #pcbassembly #electronics by @pcbforumhq

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a day ago

Two boards, both stamped "FR4" — same label, very different outcome. One survives, one comes back scrapped.  The secret is four numbers on the laminate datasheet 👇  1️⃣ Heat: Tg ≈ 140 °C softens but recovers; Td ≈ 300 °C is permanent — use 170 for lead-free 2️⃣ Dk ≈ 4.4 — that sets your impedance 3️⃣ Df ≈ 0.02 — on high-speed boards the loss eats the signal, so go low-loss 4️⃣ CTI: standard ≈ 175 V; a 400 V grade lets you pack traces tighter  The label says FR4 — but only the numbers decide whether your board survives. #pcb #pcbdesign #hardwareengineering #electronicsengineering #pcbmanufacturing #dfm #electronics by @pcbforumhq

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2 days ago

Ever shipped a board that looked perfect on screen — only to have a via open up after thermal cycling?  CAM measured this one: six via numbers came back too tight, each one an open circuit waiting.  Here are the 6 numbers that keep a via from going open 👇  1️⃣ Finished hole: don't drill below 0.15 mm 2️⃣ Annular ring: leave 2 mil — drill drift can't break it 3️⃣ Aspect ratio (thickness over hole): under 8:1 4️⃣ Plated barrel: at least 20 µm of copper 5️⃣ Laser microvia: ratio 1:1 — 0.75 is safer 6️⃣ Via-to-via: keep them 0.25 mm apart  These are typical values — check your fab's capability table before you lock the design. #pcb #pcbdesign #pcbmanufacturing #hardwareengineering #electronicsengineering #dfm #electronics by @pcbforumhq

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3 days ago

I keep seeing the same puzzling thing. A product gets crammed on two layers, the designer is proud of how tight it is - and then it fails EMC twice. How does a board that clever get sent back?I traced it. The traces look fine. The problem is under one: a return current that can't get home.Every high-speed trace has its return current right underneath it. But on his board the ground is just chopped-up scraps, so the current wanders the whole board in a big ugly loop.A loop is an antenna. That's what kills EMC.Now put the same trace on four layers. Under it is one solid ground plane, and the current tucks right under and runs straight home. The loop basically vanishes - radiation drops about 15, 20 decibels.Force two layers and you pay another way: zero-ohm jumpers, a BGA you can't fan out, and an EMC respin that costs more than just adding the layers.Layers aren't a contest. They follow density, return paths, impedance and power. Odd stacks bend when they cool, so a five-layer board often ships as six.Only a flex if it passes first time. #pcb #pcbdesign #hardwareengineering #electronicsengineering #emc #groundplane #pcbmanufacturing by @pcbforumhq

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7 days ago

Ever sent a board that looked perfect on screen — and got an engineering query back instead of a ship date?  Our CAM engineer measured this one: eight gaps came back too tight, each one a delay waiting.  Here are the 8 minimum clearances we check before your board hits the line 👇  1️⃣ Trace to trace: 4 mil on 1 oz copper — 5 on 2 oz, 8 on 3 oz 2️⃣ Hole size: 0.2 mm drilled, 0.1 mm for a laser via 3️⃣ Annular ring: 0.2 mm, or a drifting drill breaks the pad 4️⃣ Pad to pad: 0.2 mm — any tighter, solder bridges them in reflow 5️⃣ Live copper 0.3 mm from the edge (the router bites); big pours back 0.5 mm 6️⃣ Hole to copper: 8 mil 7️⃣ Trace to pad: 8 mil safe, 4 mil the floor 8️⃣ Silkscreen: keep it off the pads — ink on copper, solder won't wet  These are typical values — confirm them with your fab, and widen for high voltage per IPC-2221.  Save this before your next layout 📌
#pcb #pcbdesign #dfm #hardwareengineering #electronicsengineering #pcbmanufacturing #elections by @pcbforumhq

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9 days ago

You ordered 4 layers. It looked more pro on the quote - and it came back doing the exact same job a 2-layer board would have done.So are layers just a waste? Not always - it depends on one thing: a fast signal's return path.Every high-speed signal needs its return current to flow directly underneath it. On a 2-layer board that current often hits broken ground. It can't go straight, so it loops around the whole board - and that loop is an antenna. That's how EMC fails.A 4-layer stack-up (signal-ground-power-signal) adds one solid inner ground plane. The same return current now runs straight home under the trace, and the radiating loop nearly disappears.That plane is the only real reason to add layers - it needs extra inner-layer imaging and pressing, so cost and lead time step up. Simple boards don't need it. Fast boards can't live without it.At our fab, we'd rather tell you "two layers is enough" than sell you layers you don't need - less risk, a fairer price.Are you deciding between 2 and 4 layers right now? What's on your board?#pcb #pcbdesign #hardwareengineer #electronicsengineering #pcbmanufacturing #emc #groundplane #pcbstackup by @pcbforumhq

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10 days ago

You drew a 5-mil mask bridge between fine-pitch pins. The copper etched perfectly — but the green bridge collapsed, and the pads shorted.

If the copper survived at 5 mil, why did the bridge fail?

Because solder mask and copper are made two different ways. Copper is etched, which holds very fine detail. Solder mask is printed — LPI ink is screen-printed onto the board — so it runs coarser.

On 1-ounce copper, green mask can just reach about a 4-mil bridge at the process limit, but that‘s the edge. For safe production you give a fine-pitch bridge about 6 mil, or the ink smears across the gap and the pads short. Other mask colors, and heavier 2-ounce copper, need a wider opening again.

Our CAM team measures every bridge before the ink goes down; the thin ones get flagged or an engineering question before they ever reach the screen-printer.

Have you ever had a mask bridge collapse?#pcb #hardwareengineering #electronics #soldermask by @pcbforumhq

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16 days ago

Ever placed a plain mounting hole — no copper, no signal — and got the board back with a shiny copper barrel inside the hole, peeling after reflow?

Here‘s where that copper comes from.

Every drill tool in your fab drawing carries one plating flag: plate the wall, or leave it bare. On this hole the flag was left blank.

On most fabs, a blank flag doesn’t mean ”no copper“ — on a 2+ layer board it defaults to PTH, a plated-through hole. The hole is drilled before the electroless-copper bath, so metal grows on the wall whether you asked for it or not. After reflow, that unwanted barrel can peel and lift.

A non-plated hole (NPTH) is drilled after plating, or masked, so the wall stays bare.

Our CAM team checks every drill tool against the pads before copper — that‘s where a hole meant to stay bare gets caught.

Have you ever had a mounting hole come back plated? 👇 by @pcbforumhq

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17 days ago

Here’s what we tell engineers ordering gold fingers: two identical boards can leave the line with different bills, and the cheaper one cuts no corners.

Both boards start the same — fingers electroplated with hard gold for thousands of plugs. The split happens on the ordinary pads between them.

Board B takes OSP, an ultra-thin organic film that locks onto copper, not gold. Its fingers ride through the last bath untouched, then the rinse carries the film away. No tape, no peeling, no re-cleaning.

Board A takes immersion silver. That bath can‘t touch gold contacts, so every finger is taped before the bath and peeled after — three handlings B never pays for.

Simple rule: OSP guards copper pads, never contacts. Fewer steps, less handling, a smaller bill. Once the bag opens, assemble fast.

Do you spec OSP or immersion silver on gold-finger boards? 👇#pcb #pcbdesign #hardwareengineering #goldfinger #electronicsengineering by @pcbforumhq

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20 days ago

POV: your circuit is the only thing that survives. 🧪
A blank PCB is solid copper edge to edge — but your design only needs the wires, so everything else has to come off.
Watch one board get “dressed” in a blue light-sensitive dry film, have its traces drawn by UV light through the Gerber (the lit film hardens like armor), get developed in a soda-ash wash, etched in cupric chloride (the acid eats only the bare copper), then “undressed” as the film strips away.
Develop → Etch → Strip is one continuous pass called DES. Light chose what survived; chemistry removed the rest.
What should we “undress” next? 👇#pcb #pcbdesign #electronics #engineering #circuitboard by @pcbforumhq

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22 days ago

You draw a 5.0-mil trace. It comes back from the factory at 4.3 — no error flag, nobody touched your file. 🫣

Follow that one trace into the etcher: the chemistry bites sideways under the resist (that’s undercut), the cross-section turns trapezoidal, and on thick copper a 3–4 mil line can etch clean open.

Then the twist: before etching, CAM quietly widens the trace by exactly what the bath steals — so it lands back at 5.0.

Three designer moves: no fine lines on heavy copper, spec FINISHED width (not Gerber) on impedance layers, and ask your fab for their etch factor.

What‘s the finest trace on your boards — and the copper weight? 👇#pcb #pcbdesign #hardwareengineering #dfm #pcbmanufacturer by @pcbforumhq

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24 days ago

Why One PCB Has 3 Different Gold Finishes? #pcb #pcbdesign #electronics #goldfinger #hardwareengineering by @pcbforumhq

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a month ago